In standard, single poly CMOS (complementary metal oxide semiconductor) processes, gate capacitors are capacitive elements with large capacitances. These capacitors possess the desired gate capacitance, but also have parasitic capacitances, which are associated with diode elements, such as wells and diffusions.
An example of a MOS capacitor 10 is shown in FIG. 1. The MOS capacitor 10 includes a conductive layer 11 disposed on a gate oxide 12 disposed over a semiconductor substrate having two n+ diffusions 14 contacting an N-well 16 that overlies a P-substrate 18. The anode of MOS capacitor 10 is the gate terminal, i.e., the terminal connected to the conductive layer overlaid on the gate oxide 12. The two n+ diffusions 14 form the cathode (source-drain).
When a positive voltage is applied to the anode, an accumulation layer forms at the gate oxide—semiconductor junction, and the capacitance is the gate capacitance. It is also possible to achieve the same capacitance by making the two diffusions p+, and having a separate n+ contact to the well (not shown), making it an accumulation capacitor. Both types of capacitors exhibit essentially the same capacitance once the Vg (gate potential, or anode/cathode potential) is above the threshold voltage for the capacitor. The MOS capacitor 10 also exhibits a parasitic capacitance at its cathode, which is caused by a parasitic diode capacitor 20 formed between the N-well 16 and substrate 18. The parasitic diode capacitor 20 is determined by the area and space-charge layer thickness of the diode, and may be 20% of the gate capacitance.
Such MOS capacitors are utilized in a variety of analog circuits, such as charge pumps. A four phase Dickson-type charge pump is shown in FIG. 2, while a single pump stage is shown in FIG. 3. U.S. patent application 2002/0145464, entitled “Charge Pump Stage with Body Effect Minimization”, which is incorporated herein in its entirety by reference, provides an explanation how the charge pump and the single stage operates. A brief explanation is now provided in the following paragraphs, with reference to FIGS. 2 and 3.
A charge pump typically comprises cascaded stages that progressively boost the voltage to higher levels. The charge pump functions by progressively storing more charge on a capacitor which is part of a capacitor-diode combination, with several such stages being placed together in a network to obtain the desired increase in voltage. The diode functions to prevent discharge of the capacitor prior to placing the additional charge thereon.
The charge pump circuit of FIG. 2 includes a plurality of charge transfer transistors (reference letters m(i)) connected in series. In FIG. 2, four such charge transfer transistors are shown, labeled m1, m2, m3 and m4. The charge transfer transistors may use, but are not limited to, CMOS technology, being either n-channel or p-channel (NMOS or PMOS) field effect transistors (FETs). NMOS is generally used to pump positive voltages (this is the case illustrated in FIG. 2), whereas PMOS is generally used to pump negative voltages. The MOSFETs have a control electrode (e.g., gate), a first electrode (e.g., drain) and a second electrode (e.g., source), connected to nodes, as described hereinbelow. (Since MOSFETs are typically symmetrical components, the true designation of “source” and “drain” is only possible once a voltage is impressed on the terminals of the transistors. The designations of source and drain throughout the specification should be interpreted, therefore, in the broadest sense.) Preferably, the bulks of the charge transfer transistors mi are coupled to a reference line (not shown for the sake of simplicity) for receiving a reference voltage, generally ground in the case of NMOS.
The source of charge transfer transistor m1 is connected to node n0, which is connected to Vdd. The gate of charge transfer transistor m1 is connected to node g1, and the drain is connected to node n1. The source of charge transfer transistor m2 is connected to node n1, the gate is connected to node g2, and the drain is connected to node n2. The source of charge transfer transistor m3 is connected to node n2, the gate to node g3, and the drain to node n3. Likewise, the source of charge transfer transistor m4 is connected to node n3, the gate to node g4, and the drain to node n4.
Two-phase, non-overlapping pulse trains PH1 and PH2 are provided, such as from a pulse generator (not shown). By non-overlapping it is meant that 0-to-1 and 1-to-0 voltage transitions of one pulse never overlap with the transitions of the other pulse. The PH1 and PH2 phases inject energy into the pump through large capacitors C1, C2, C3 and C4 into nodes n1, n2, n3 and n4, respectively. The charge is transferred along the pump through charge transfer transistors m(i) connecting node n(i) to node n(i+1).
Similarly, two-phase, non-overlapping pulse trains PH1A and PH2A are also provided. The PH1A and PH2A phases inject energy into the pump through small capacitors C1A, C2A, C3A and C4A into nodes g1, g2, g3 and g4, respectively. Capacitors C1A, C2A, C3A and C4A preferably have a much smaller capacitance than large capacitors C1, C2, C3 and C4.
A plurality of auxiliary transistors ti (i.e., t1, t2, t3 and t4) may be provided. Each auxiliary transistor t(i) has its drain connected to the gate node g(i) of each charge transfer transistor m(i) (i.e., m1, m2, m3 and m4, respectively). The source of each auxiliary transistor t(i) is connected to the source of each charge transfer transistor m(i) (i.e., node n(i−1)). The gate of each auxiliary transistor t(i) is connected to the drain of each charge transfer transistor m(i) (i.e., node n(i)). The bulk of each auxiliary transistor t(i) is connected to the bulk of each charge transfer transistor m(i), which is generally grounded. The auxiliary transistors t(i) and the PH1A and PH2A phases control the gate voltage of the charge transfer transistors m(i).
The operation of the first stage of the pump is now explained, with all subsequent stages operating in the same manner. The operation commences with the PH1 phase starting to rise. Initially, charge transfer transistors m1 and m2 are non-conducting (i.e., turned off), since the PH1A and PH2A phases are in their low phase. The PH1 phase then fully rises and injects energy into node n1, raising (or “pushing”) node n1 to a voltage boosted above Vdd, such as 2Vdd. The rise of node n1 forces node g1 to Vdd through auxiliary transistor t1. Since the source of charge transfer transistor m1 is connected to Vdd at node n0, the gate-source voltage bias Vgs of charge transfer transistor m1 is zero, assuring that transistor m1 is turned off.
After a short time, typically in the order of several nanoseconds, the PH1A phase rises, which makes charge transfer transistor m2 conduct (i.e., turns on). During this time, node n1 is at a higher voltage than node n2. Since, as just mentioned, charge transfer transistor m2 is conducting, charge is transferred from node n1 to node n2. During the next phase, the PH2 phase rises and the PH1 phase drops. This causes node n1 to drop and node n2 to rise, thereby causing charge to be transferred from node n2 to node n3. In this manner charge is transferred along the pump. Each of the g(i) nodes is raised by Vdd with respect to the n(i) nodes when charge transfer is taking place. In the latter stages of the pump, the source and drain nodes (i.e., nodes n3 and n4) are raised well above the bulk, which is usually grounded.
Accordingly, in the charge pump, energy is injected through the large capacitors C1-C4 by the oscillation of the clock signals PH1 and PH2. Referring again to FIG. 1, the cathode of the MOS capacitor 10 may be connected to one of the clocks, while the anode may be connected to the pump's interior nodes n1-n4. The oscillation of the cathode leaks current to GND through the parasitic capacitor 20. As the pump capacitors C1-C4 are very large, the parasitic currents associated with the parasitic capacitors may be a significant portion of the pump's power consumption and may range from 20-50% of the total power.